As the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. However, in order to reduce gate leakage, high dielectric constant (high-k) gate oxide layers are used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a typical gate oxide used in future technology nodes.
Additionally, as technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the typical polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming the metal gate electrode is termed “gate last” process because the final metal gate electrode is fabricated after the other transistor components, which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate.
FIG. 1 shows a cross-sectional view of a plurality of conventional gate structures for semiconductor device 100 at a fabrication stage in a “gate last” process. The semiconductor device 100 in FIG. 1 comprises a P-well region 102 and an N-well region 103 formed within a substrate. An isolation structure 104 is formed between the P-well region 102 and the N-well region 103. Gate structures 101 are formed on the P-well 102 region and the N-well region 103, respectively. The gate structures 101 include a high K dielectric layer 106 and a metal layer 107 below a dummy gate electrode 105. Spacers 108a and 108b is disposed adjacent to the gate structure 101. An interlayer dielectric layer 109 (ILD) is formed to surround the spacer 108a and 108b. A hardmask layer 110 and a photoresist layer 111 are deposited and patterned to expose the dummy gate electrode 105 in N-well region 103. An etching step is performed to remove the exposed dummy gates 105 for forming a recess for accommodating a metal gate electrode. The metal gate electrodes above the P-Well region 102 and N-well region 103 are formed separately so that the respective metal gate electrodes may be formed using different materials.
However, the dummy gate removal step presents a number of challenges. For example, the metal layer 107 at the bottom the dummy gates may be oxidized. Another example, the spacers 108a and 108b may be damaged and metal residues may be formed during the metal gate electrode formation stage. Therefore, electrical shorting and device failure could occur.
Accordingly, what is needed in the art is an improved formation method for metal gate structure, so that the device performance can be satisfied.